1. Field of the Invention
This invention is directed to batch testing of semiconductor devices.
2. Background Art
As part of the manufacture of semiconductor devices, it is desired to test the devices so that inoperative devices can be identified and disposed of. Testing can occur at many times during the process of manufacture. For example, semiconductor devices are sometimes manufactured in bulk as a plurality of die on a substrate (referred to as a "wafer"). A "grid" of devices on the wafer are created, and each die is coupled to a test circuit using probes. Inoperative or substandard die are identified by results of the testing process and are marked as "bad" or "rejected". After this initial testing, the die are individually broken off the wafer and are "packaged" in a form for distribution. At this time, the packaged devices are individually tested again so that only operative devices are delivered. This individual testing of packaged devices is time consuming. It is desired to provide a system for simultaneous testing of multiple packaged devices.
A number of prior art patents describe semiconductor device testing schemes.
U.S. Pat. No. 3,568,129 to Gold is directed to a circuit board to which a plurality of integrated circuits can be attached. At least some of the sockets for the integrated circuits are removable so that they can be interchanged with different types of sockets to accommodate a variety of integrated circuit packages. Gold does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets. The testing board is not part of the finished device.
Rattcliff et al., U.S. Pat. No. 3,860,313, describes a circuit board with a plurality of electrical component receiving locations for packaged integrated circuits. The board includes a plurality of parallel recesses arranged in parallel to be used for connecting discrete electrical circuit components. Rattcliff et al. provides for the use of a clamping ring for creating a tight connection of the electric circuit component leads against the conductive material in the recesses. Rattcliff et al. does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
Hargis, U.S. Pat. No. 4,426,773, describes an array of electronic packaging substrates with each one having a plurality of electrically interconnected internal and external terminals. The array has a matrix structure of lines of separation and conductors to allow for the attachment of electronic components to the electronic packaging substrates. This configuration allows for testing of the components in an array format.
The array's connection points to external circuitry, labeled 13A, B, C, D in FIG. 4 are not of the edge connector type, rather they are contact pads. The external connection pads are of the type that contact point connection, perhaps using a probe similar to a wafer sort probe, rather than an edge connector type external connection. The arrays matrix does not allow for individual testing without first breaking the substrate into individual sections, at which time it cannot be put back together for further stress testing.
U.S. Pat. No. 4,689,103 to Elarde is directed to a method of processing an array of injection molded plastic substrates to form electronic circuits. Elarde provides that the plastic substrates are injection molded separately and then physically connected to a common planar array using a carrier board with receptacles. Each of the substrates having metal deposited in its pattern of channels. Electronic circuits may then be formed on each of the substrates in the planar array by stuffing the array with electronic components using an automatic insertion machine. Elarde does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
U.S. Pat. No. 4,870,356 to Tingley is directed to a universal test fixture for electrically connecting a plurality of component pins to compute test logic without the need for specialized sockets. The test fixture comprises a planar dielectric substrate having a multi-conductor pattern on the top surface comprising a plurality of equal width, equal spaced conductor bars, and including electrical conductors for connecting the spaced conductor bars to test logic. A resiliently deformable member or material enables the fixture to compensate for varying planarity between the tips of the component pins to be tested. Tingley does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
Eichelberger et al., U.S. Pat. No. 4,937,203, is directed to a removable polymer film with a metallization layer that is used to test a plurality of unpackaged interconnected integrated circuit devices mounted on a substrate. The metallization layer on the film is used to connect the circuits with a minimum of capacitive loading. A plurality of films may be used to allow the circuit to be tested in a plurality of configurations. Eichelberger et al. provides a test integrated circuit device disposed on the substrate to drive at least some of the plurality of devices. Eichelberger et al. does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
U.S. Pat. No. 4,926,117 to Nevill is directed to a two-piece burn-in board which has an ability to act as a standard burn-in board, in which all devices on the board share common signals. The board can be disassembled so that it has the ability to act as a device carrier wherein each individual device is completely isolated and has a standard burn-in board wherein all devices share the common signals. Nevill is directed to use with packaged integrated circuit devices, and for this reason among others Nevill does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
U.S. Pat. No. 4,968,931 to Littlebury et al. describes a method of burning in integrated circuits on a semiconductor wafer using a flexible membrane probe enclosed in a chamber. The flexible membrane probe is sized so that it can couple to a plurality of points on the wafer and is connected to external circuitry to drive the integrated circuits on the wafer in parallel. A bladder, which lies behind the membrane probe is inflated to cause the probe to couple to each of the contact pads on the wafer. Littlebury et al. uses a flexible membrane to couple to a semiconductor wafer, and for this reason among others it does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
Chang, U.S. Pat. No. 5,031,073, is directed to a method and apparatus for fault isolation on a circuit board. The method use a printed circuit board that is partitioned into a plurality of circuit regions which are selectively isolated with respect to input and output signals. The fault in the circuit is then identified using provided techniques for connecting and isolating the partitioned circuits. Chang describes the use of a circuit board with attached packaged integrated circuits and which is designed to allow for easy of isolation and reconnection of each partition, for these reasons among others Chang does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
Ewers, U.S. Pat. No. 5,175,491, describes a test fixture for simultaneously performing burn in and testing of multiple packaged integrated circuit devices. The packaged integrated circuits rest on electrical contacts without sockets. A top plate and a compressible material are used to accommodate variations in package size and still provide for contact to the leads. Ewers is directed to the testing of packaged devices in an external carrier mechanism, and for this reason among others Ewers does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.
U.S. Pat. No. 5,180,974 to Mitchell et al. is directed to an integrated system for testing, marking, inspecting, and shipping completed semiconductor integrated circuit parts in a modified standard shipping tray by the combined use of a novel tray cover and an appropriately designed burn-in board assembly. The burn-in board is designed for packaged integrated circuit packages, and for this reason among others does not teach the use of edge connectors created on a substrate sheet to enable the batch testing of surface mount devices using substrate sheets.